1. The Anatomy of a Digital Delay

Unlike continuous analog controllers (pneumatic, op-amp), a PLC operates in discrete time steps. This quantization of time introduces unavoidable delays that act as pure dead time in the control loop. The total delay is not just the scan time; it is a sum of several asynchronous components.

• Input Latency: Time for the A/D converter to digitize the signal (often 10-100ms depending on the module filter settings) plus the bus transmission time to the CPU.
• Program Execution ($T_{scan}$): The time it takes the CPU to solve the PID algorithm. In a continuous task (OB1), this varies with code load. In a cyclic task (OB35), it is fixed but acts as a sample-and-hold delay.
• Output Latency: Time to write the result to the output card, plus the D/A conversion time, plus the actuator response time.

The "One-Cycle" Myth: Many engineers assume the delay is just the scan time. In reality, due to the asynchronous nature of inputs vs program vs outputs, the statistical average delay is often closer to 1.5 to 2.0 times the scan time plus jitter. This tool calculates the Effective Dead Time ($D_{eff}$) based on these factors.

2. Phase Lag: Why Fast Loops Destabilize

Dead time is the enemy of feedback control because it creates Phase Lag ($\phi$). Phase lag grows linearly with frequency ($f$).

Consider a Flow Loop oscillating at 1 Hz ($T=1s$). If your PLC introduces a total effective delay of 100ms (0.1s), you introduce an extra phase shift of:

$$ -360 \times 1 \times 0.1 = -36^\circ $$

A robust PID loop typically has a Phase Margin of about 45°. If you subtract 36° from that margin, you are left with only 9°. The loop becomes barely stable, ringing excessively after any setpoint change. If the delay increases slightly (e.g., network traffic increases jitter), the loop will go unstable.

3. Aliasing: The "Ghost Signal" Problem

Digital sampling creates a unique problem called Aliasing. According to the Nyquist-Shannon Sampling Theorem, you must sample a signal at least twice as fast as its highest frequency component ($f_s > 2 f_{max}$).

If your pressure transmitter has noise at 10 Hz (from pump pulsation), but your PLC scans at 50ms (20 Hz), you are right on the limit. If the noise shifts to 15 Hz, your 20 Hz sampler will "see" a ghost signal at 5 Hz ($20 - 15 = 5$).

The PID controller will try to fight this 5 Hz "ghost" oscillation, moving the valve unnecessarily. This wears out the valve packing and destabilizes the process. Solution: Always ensure your scan rate is 5x to 10x faster than the process dynamics, or use analog low-pass filters on the input cards.

4. Jitter: Variance is Worse than Latency

Jitter is the variation in loop execution time. A loop running exactly every 100ms is easier to tune than a loop running at 10ms +/- 8ms.

Why? PID derivative action ($D$) relies on $\Delta Error / \Delta Time$. If $\Delta Time$ fluctuates randomly due to jitter, the calculated Derivative kick fluctuates wildly, injecting noise into the output. This is why derivative action is often turned off in PLCs with poor determinism (Continuous Task loops).

Best Practice: Always put PID loops in a Cyclic Interrupt / Periodic Task (e.g., OB30/35 in Siemens, Periodic Task in Rockwell). This enforces a fixed $\Delta T$, eliminating calculation jitter.

5. Tuning for Digital Delays

If you cannot speed up the PLC (e.g., large legacy system), you must detune the loop. The added digital dead time ($\theta_{dig}$) adds to the process dead time ($\theta_p$).

Using the Lambda tuning rule (where closed loop time constant $\lambda$ is chosen based on dead time), the maximum aggressive gain is inversely proportional to the total dead time:

If digital delay adds 20% to your total dead time, you must reduce your Controller Gain ($K_c$) by roughly 20% to maintain the same stability margin. This tool calculates that specific Detune Factor for you.